Back to the Future: Rethinking EDA Infrastructure for Agentic Systems in Chip Design Verification

Problem

This work addresses a significant gap in Electronic Design Automation (EDA) workflows, specifically in the areas of post-simulation verification and interactive waveform debugging. The authors highlight the limitations of existing methodologies in effectively managing and interpreting simulation data, which is crucial for ensuring the correctness of chip designs. The paper is a preprint and has not yet undergone peer review.

Method

The authors propose a novel framework named Back-to-the-Future (BTTF) that integrates several key components to enhance the verification process:

• Data Processing: BTTF distills unstructured simulation dumps into a normalized relational SQLite database, facilitating easier access and manipulation of simulation data.
• Orchestration Engine: The framework employs a collaborative multi-agent system that allows for distributed processing and interaction among agents, improving the efficiency of the verification tasks.
• Query Translation: BTTF includes a mechanism for converting natural-language verification queries into schema-aware SQL, enabling users to interact with the database using intuitive language rather than complex query syntax.
• Signal Correlation: The framework correlates signal anomalies detected during simulations with versioned Register Transfer Level (RTL) repositories, aiding in the identification of potential design flaws.

Results

The BTTF framework achieves an execution accuracy of 95.33%, significantly outperforming existing studies that target static RTL code generation, which report an accuracy of only 74.6%. This improvement demonstrates the effectiveness of the proposed approach in enhancing verification accuracy in chip design workflows.

Limitations

The authors do not report any limitations in their study. However, as with any novel framework, potential challenges may arise in terms of scalability, integration with existing EDA tools, and the adaptability of the multi-agent system to various design environments, which are not explicitly discussed in the paper.

Why it matters

The implications of this work are substantial for downstream applications in chip design verification. By improving the accuracy and efficiency of post-simulation verification processes, the BTTF framework has the potential to reduce time-to-market for semiconductor products and enhance the reliability of complex chip designs. Furthermore, the integration of natural language processing for query translation could democratize access to verification tools, allowing engineers with varying levels of expertise to engage with the verification process more effectively.