Design Conductor 2.0: An agent builds a TurboQuant inference accelerator in 80 hours

Problem
This paper addresses the limitations of previous automated design systems for hardware accelerators, specifically focusing on the capability gap in generating complex designs autonomously. The authors build upon their prior work, “Design Conductor,” which could create a RISC-V CPU in 12 hours, by introducing an updated multi-agent system that leverages advancements in large language models (LLMs) released in April 2026. This work is presented as a preprint and has not yet undergone peer review.

Method
The core technical contribution is the enhanced multi-agent harness that utilizes frontier LLMs to autonomously design hardware accelerators. The system can now handle tasks 80 times larger than its predecessor while achieving higher quality outputs. The authors detail the design of “VerTQ,” an LLM inference accelerator that incorporates TurboQuant support within a 240-cycle pipeline. The architecture features 5129 FP16/32 processing units and is optimized for FPGA implementation at 125 MHz, occupying 5.7 mm² in TSMC 16FF technology with eight attention pipes. The training compute specifics are not disclosed, but the authors emphasize the efficiency of token usage and empirical characteristics of the design process.

Results
The VerTQ design demonstrates significant improvements over previous baselines, achieving a 240-cycle pipeline with a high degree of parallelism and processing capability. While specific numerical performance metrics (e.g., throughput, latency) against established benchmarks are not provided in the abstract, the authors claim that the new system operates at a substantially higher quality level than prior designs. The paper suggests that the advancements in design quality and task complexity are notable, although exact effect sizes are not quantified.

Limitations
The authors acknowledge several limitations, including the reliance on the latest LLMs, which may not generalize well to future models or tasks outside the scope of their training. Additionally, the paper does not address potential scalability issues when applying the system to even larger designs or different hardware architectures. The empirical analysis of token usage may also reveal inefficiencies that are not fully explored in the current work.

Why it matters
This research has significant implications for the field of hardware design automation, particularly in the context of AI-driven methodologies. By demonstrating the capability of LLMs to autonomously generate complex hardware designs, the work paves the way for future explorations into more sophisticated architectures and accelerators. The findings could influence the development of next-generation AI inference systems, potentially leading to more efficient and powerful hardware solutions. Furthermore, the approach could inspire further research into the integration of AI in hardware design workflows, enhancing the synergy between software and hardware development.

Authors: The Verkor Team, Ravi Krishna, Suresh Krishna, David Chin
Source: arXiv:2605.05170
URL: https://arxiv.org/abs/2605.05170v1