NeuroRing: Scaling Spiking Neural Networks via Multi-FPGA Bidirectional Ring Topologies and Stream-Dataflow Architectures

Problem
This preprint addresses the limitations in the scalability and efficiency of Spiking Neural Networks (SNNs) for large-scale execution. While SNNs are recognized for their energy-efficient, event-driven computation, existing hardware solutions (CPU, GPU, ASIC, FPGA) struggle with the challenges posed by sparse spike communication and synchronization overhead. The authors identify a gap in the literature regarding modular and scalable SNN accelerators that can effectively leverage programmable FPGAs while maintaining compatibility with existing SNN workflows.

Method
The core technical contribution is the NeuroRing architecture, which employs a stream-dataflow model and a bidirectional ring topology for SNN acceleration. Implemented using High-Level Synthesis (HLS) on FPGAs, NeuroRing supports both single and multi-FPGA configurations. The architecture is designed to integrate seamlessly with the NEST simulator, allowing for straightforward deployment of existing SNN models. The authors detail the modularity of the design, which facilitates scalability and adaptability for various SNN applications. The training compute requirements are not explicitly disclosed, but the architecture’s efficiency is emphasized through its real-time execution capabilities.

Results
NeuroRing was evaluated on two benchmarks: the cortical microcircuit benchmark and a Sudoku constraint-satisfaction workload. The results indicate that NeuroRing achieves a real-time factor (RTF) of 0.83 for the full-scale cortical microcircuit, demonstrating faster-than-real-time execution. The architecture exhibits strong scaling with an increase in FPGA resources, achieving a 2.5x speedup over baseline implementations on single FPGA setups. Additionally, it maintains key activity statistics consistent with the NEST reference model, showcasing its fidelity in simulating SNN dynamics. Energy efficiency metrics are reported as competitive, although specific numerical comparisons to baseline systems are not provided.

Limitations
The authors acknowledge that while NeuroRing demonstrates significant improvements in execution speed and energy efficiency, it may still face challenges in terms of programmability compared to more traditional architectures. They do not discuss potential limitations related to the complexity of the stream-dataflow model or the overhead introduced by the bidirectional ring topology. Furthermore, the scalability of the architecture beyond two FPGAs is not thoroughly explored, which may limit its applicability in extremely large-scale scenarios.

Why it matters
NeuroRing represents a significant advancement in the field of SNNs by providing a flexible and scalable platform that can bridge the gap between neuroscience simulations and broader event-driven applications. Its integration with existing SNN workflows through the NEST simulator facilitates adoption in research and practical applications. The architecture’s ability to execute large-scale SNNs efficiently opens avenues for further exploration in neuromorphic computing, potentially influencing the design of future hardware accelerators tailored for SNNs and other event-driven models.

Authors: Muhammad Ihsan Al Hafiz, Artur Podobas
Source: arXiv:2604.28059
URL: https://arxiv.org/abs/2604.28059v1